Master makegeek
I've picked up a few tricks from the project that I've been working on recently, and this latest trick with the makefile is especially cool. It started with the style of putting all the object files in a subdirectory so they didn't clutter up the source directory. This was nice, but not quite rocket science. I did have to switch build pattern rules style from traditional to the GNU style, so instead of:

.c.o:
   $(CC) $(CFLAGS) -c -o $@ $<
.cpp.o:
   $(CXX) $(CXFLAGS) -c -o $@ $<

I now had:

$(OBJ)/%.o: %.cpp
   $(CXX) $(CXXFLAGS) -c -o $@ $<
$(OBJ)%.o: %.c
   $(CC) $(CFLAGS) -c -o $@ $<

But I really hated putting together a list of the object files with the sub-directory in front. I tried using a really short variable name, but it was still ugly:

OD= obj
OBJ= $(OD)/hm_core.o $(OD)/hconf_core.o $(OD)/hconf_module.o $(OD)/hm_config.o ...

Ugly, but isn't there a better way? I asked around originally, but not widely enough, turns out there is a way:

OD= obj
OBJ= hm_core.o hconf_core.o hconf_module.o hm_config.o ...

BUILD_OBJ= $(addprefix $(OD)/,$(OBJ))

That's just sooo cool. Almost makes me want to read the man page for GNU make(1). Oh, wait a minute, the useful information isn't in the man page. It's in this help system called info which uses emacs key bindings for navigation. So first I would have to go read the man page for info so I could use it, oh wait, the useful information isn't in the man page ...

Oh, forget it.

  ¶ 9:00 PM